1. Field of the Invention
The present invention relates generally to field effect transistors (referred to as FETS hereinafter) requiring a high breakdown voltage, and more particularly, to FETs of a high breakdown voltage type having stable electrical characteristics.
2. Description of the Prior Art
An analog circuit and an analog switch in a CMOS (complementary metal oxide semiconductor) require a high breakdown voltage. The reason for this is that the effect of noise is reduced if an operating voltage is high when the analog circuit includes noise.
FIG. 1 shows an example of an MOS transistor having a high breakdown voltage. The transistor is referred to as an LDD (Lightly Doped Drain) transistor. The LDD transistor comprises a P type semiconductor substrate 5, a source S and a drain D each having an N.sup.- impurity diffused layer 3 and an N.sup.+ impurity diffused layer 4 formed in the major surface of the substrate 5, and a gate G formed through an insulating film over a region interposed between the source S and the drain D. Since the LDD transistor includes the region 3 having a low concentration, occurrence of a high electric field in the vicinity of the drain D is restrained. Thus, dielectric breakdown does not easily occur in the high electric field portion which appears in the drain region.
However, in the LDD-transistor, the dimension (.DELTA.l.sub.1 in FIG. 1) of the N.sup.- region can be only slightly adjusted. The reason for this is that the gate G is provided with a sidewall or the like so that the N.sup.- diffusion region is formed. So the effect obtained by using the LDD transistor is small. Thus, if a higher breakdown voltage is required, the LDD transistor is not employed. More specifically, in a transistor having a higher breakdown voltage, the N.sup.- diffusion region must be formed by mask alignment.
FIG. 2A is a plan view showing the conventional FET having a high breakdown voltage, and FIG. 2B is a cross sectional view of a portion along a line IIB--IIB shown in FIG. 2A. Referring to FIGS. 2A and 2B, the conventional FET having a high breakdown voltage comprises a P type semiconductor substrate 5, a source S and a drain D formed in the major surface of the semiconductor substrate 5, and a gate electrode G formed through an insulating, film 2 over a region interposed between the source S and the drain D. In general, the gate electrode G is formed of polysilicon (polycrystalline silicon) and the insulating film is formed of a silicone oxides film. The gate electrode of polysilicon, the silicon oxide film and the semiconductor substrate constitute a so-called MOS structure (generally referred to as MIS structure). The source S and the drain D each have a double diffusion layer comprising an N.sup.- diffusion region 3 having a low n-type impurity concentration and an N.sup.+ diffusion region 4 having a high n-type impurity concentration. The source S and the drain D are connected to an aluminum interconnection 7, respectively. The entire FET is separated from the other elements by a field oxide film 6.
As is shown in the drawing, the source S and the gate G have prescribed width of N.sup.- diffusion regions 3, t.sub.S and t.sub.D.
Description is now made of the reason why the above described FET having the double diffusion layer has a high breakdown voltage.
FIG. 3A is a typical diagram showing a transistor having a double diffusion layer, and FIG. 3B is a typical diagram showing a transistor having only an ordinary N.sup.+ diffusion layer. Description is made on the case in which an N.sup.+ type diffusion layer is formed in the major surface of the P type semiconductor substrate. Referring to FIG. 3B, in the ordinary transistor, a positive potential is applied to the gate G and the drain D, and the source is grounded. At that time, a depletion layer (represented by a dotted line in FIG. 3B) expands into the substrate and the N.sup.+ diffusion region 4. The depletion layer freely expands into the substrate but hardly expands into the N.sup.+ diffusion region 4 because a large amount of electrons exist therein. As a result, breakdown occurs.
On the other hand, if there is a relatively large dimension (.DELTA.l.sub.2 in FIG. 3A) between the N.sup.- diffusion region layer and the N.sup.+ diffusion region, the depletion layer may expand into not only the substrate but also the direction of the N.sup.+ diffusion region. As a result, the breakdown voltage rises.
Thus, if the N.sup.- diffusion region is provided around the N.sup.+ diffusion region, not only the breakdown voltage rises but also considerable gain is obtained. The reason for this is that the resistance of the N.sup.- diffusion region is too high. In other words, the resistance of the FET with both high and low impurity concentration region is much less than that with only low density region. The dimension .DELTA.l.sub.2 (in FIG. 3A) is substantially larger than the dimension .DELTA.l.sub.1 (see FIG. 1) in the above described LDD transistor. Thus, the transistor of a high breakdown voltage type shown in FIG. 2 has a substantially larger breakdown voltage (for example, approximately 18 V) than that of the LDD transistor.
FIGS. 4A to 4I are diagrams showing the sequential steps of the manufacturing process of the conventional FET of a high breakdown voltage type. Referring to FIGS. 4A to 4I, description is made on the manufacturing process of the conventional FET of a high breakdown voltage type. A P type silicon substrate 5 is prepared. A double film comprising a silicon oxide film 21 and a silicon nitride film 22 is formed on the major surface thereof (in FIG. 4A). A photoresist 23 is formed on the silicon nitride film 22, to be patterned (in FIG. 4B). The silicon substrate 5 is thermally oxidized, so that a field oxide film 6 is formed (in FIG. 4C). A silicon nitride film 24 is removed. A polysilicon layer 25 is formed on the silicon oxide film 21 (in FIG. 4D), to be patterned as a gate G. Arsenic, for examples is ion-implanted from above the substrate 5 utilizing a polysilicon gate G and the field oxide film 6 as a mask, so that an N.sup.- diffusion region 4 is formed in the major surface of the substrate 5 (in FIG. 4E). A silicon oxide film 26 is formed on the major surface of the substrate 5, the gate G and the field oxide film 6 (in FIG. 4F). A mask layer 27 is formed in a predetermined position on the silicon oxide film 26. Arsenic, for example, having a higher concentration than that in the last ion implantation are ion-implanted from above the mask, so that the N.sup.+ diffusion region 4 is formed in an N.sup.- diffusion region 3 (in FIG. 4H). Aluminum interconnections are connected to a sources S and a drain D each comprising the N.sup.+ diffusion region 4 and the N.sup.- diffusion region 3 and the gate G respectively (in FIG. 4I).
The conventional FET of a high breakdown voltage type is manufactured by the foregoing process. The N.sup.+ diffusion layer is formed by mask alignment (in FIG. 4G). Thus, when an error of mask alignment occurs, the position of the N.sup.+ diffusion region 4 is shifted. As a result, the dimension (.DELTA.R and .DELTA.L in FIG. 4H,) on the side of the gate of the N.sup.- diffusion region 3 may not be equal.
FIG. 5 is a diagram showing an equivalent circuit of the conventional FET of a high breakdown voltage type shown in FIGS. 2A and 2B. Referring to FIG. 5, the equivalent circuit of the conventional FET of a high breakdown voltage type comprises resistances R.sub.D and R.sub.S on the side of the drain, D and the source S, respectively. The reason for this is as follows: There exists an N.sup.- diffusion region having a low impurity concentration between the drain D and the source S. Since the impurity concentration of the N.sup.- diffusion region is low, the electric resistance thereof is high. As a result, when a current I.sub.DS flows between the source S and the drain D, the resistance can not be neglected. Thus, a substantial voltage V.sub.DS between the drain D and the source S and a substantial voltage V'.sub.GS between the gate G and the source S are affected by the voltage drop caused by the resistances R.sub.D and R.sub.S. In general, assuming that an on-voltage of the MOSFET is represented by V.sub.TH, the current I.sub.DS flowing between the drain D and the source S of the MOSFET is represented by the following equation: EQU I.sub.DS .apprxeq.K(V'.sub.GS -V.sub.TH).sup.2 ( 1)
The equation (1) is described in "MOSFET in Circuit Design", R. H. Crawford Texas Instruments Electronics Series McGRAW HILL, pp. 51. Thus, the voltage drop caused by the resistances R.sub.D and R.sub.S also affects the current I.sub.DS. Symbol K in the equation (1) is the constant.
Referring now to FIG. 5, description is specifically made of the effect on the current I.sub.DS. For of illustration, let V.sub.TH =0.5 V. It is assumed that the voltage V.sub.GS of 5 V is applied between the gate G and the source S in order to reverse a channel. At that time, the current I.sub.DS flows between the source S and the drain D, so that the voltage drop caused by the resistance R.sub.S is developed. Assuming that the voltage drop caused by the resistance. R.sub.S, i.e., (I.sub.DS .multidot.R.sub.S) is 0.5 V, a substantial voltage V'.sub.GS of the transistor is equal to V.sub.GS -I.sub.DS .multidot.R.sub.S. More specifically, without the resistance R.sub.S, I.sub.DS .apprxeq.K(5-0.5).sup.2 .apprxeq.20K. However, I.sub.DS .apprxeq.K(4.5-0.5).sup.2 .apprxeq.16K due to the resistance R.sub.S. Since I.sub.DS is proportional to the second power of (V'.sub.GS -V.sub.TH), the resistance R.sub.S significantly affects the current I.sub.DS.
As can be seen from the foregoing, in order to obtain an MOSFET having stable electrical characteristics, it is important to decrease the variation in the widths t.sub.D and t.sub.S (in FIG. 2B) of the N.sup.- diffusion region 3 on the side of the channel region, since the N.sup.- diffusion region 3 has high electric resistance as much as possible.
In such an MOSFET, the N.sup.- diffusion region 3 is formed in the exact position by the gate electrode G and field mask 6 (see. FIG. 4E). On the other hand, the N.sup.+ diffusion region 4 is formed by mask alignment (see FIG. 4G). As a result, the position where the N.sup.+ diffusion region 4 is formed, can be shifted by the error of mask alignment. Thus, the N.sup.+ diffusion region 4 is formed, shifted left (in the direction represented, by an arrow X in FIG. 2B), for example, the width t.sub.D on the side of the gate G of the N.sup.- diffusion region 3 included in the drain D is decreased (t.sub.D') while the width t.sub.S on the side of the gate G of the N.sup.- diffusion region 3 included in the source S is increased (t.sub.S'). In this state, the resistance R.sub.D is decreased while the resistance R.sub.S is increased, in FIG. 5. As a result, the voltage drop caused by the resistance R.sub.S is increased, so that the voltage V'.sub.GS between the gate G and the source S is decreased. Consequently, the current I.sub.DS given by the equation (1) is decreased. Contrary to this, if the N.sup.+ diffusion region 4 is formed, shifted right, the current I.sub.DS is increased.
As described in the foregoing, the MOSFET having the structure as shown in FIGS. 2A and 2B has a high breakdown voltage. On the other hand, the current flowing therein, or the like is affected by the error of mask alignment. As a result, it is difficult to provide an MOSFET having stable electrical characteristics.